Regviz

NXP Semiconductors /LPC15xx /SCTIPU /SAMPLE_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SAMPLE_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC15xx/SCTIPU/SAMPLE_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SAMPE_IN_A0_SELECT_)IN0SEL 0 (SAMPE_IN_A1_SELECT_)IN1SEL 0 (SAMPE_IN_A2_SELECT_)IN2SEL 0 (SAMPE_IN_A3_SELECT_)IN3SEL 0 (SELECTS_SAMPLE_ENABL)SAMPLE_EN0SEL 0 (SELECTS_SAMPLE_ENABL)SAMPLE_EN1SEL 0 (SELECTS_SAMPLE_ENABL)SAMPLE_EN2SEL 0 (SELECTS_SAMPLE_ENABL)SAMPLE_EN3SEL 0 (TRANSPARENT_MODE_SA)LATCHEN0 0 (TRANSPARENT_MODE_SA)LATCHEN1 0 (TRANSPARENT_MODE_SA)LATCHEN2 0 (TRANSPARENT_MODE_SA)LATCHEN3

IN3SEL=SAMPE_IN_A3_SELECT_, IN1SEL=SAMPE_IN_A1_SELECT_, LATCHEN2=TRANSPARENT_MODE_SA, SAMPLE_EN3SEL=SELECTS_SAMPLE_ENABL, SAMPLE_EN0SEL=SELECTS_SAMPLE_ENABL, LATCHEN1=TRANSPARENT_MODE_SA, LATCHEN3=TRANSPARENT_MODE_SA, LATCHEN0=TRANSPARENT_MODE_SA, SAMPLE_EN2SEL=SELECTS_SAMPLE_ENABL, SAMPLE_EN1SEL=SELECTS_SAMPLE_ENABL, IN2SEL=SAMPE_IN_A2_SELECT_, IN0SEL=SAMPE_IN_A0_SELECT_

Description

SCT IPU sample control register. Contains the input mux selects, latch/sample-enable mux selects, and sample overrride bits for the SAMPLE module.

Fields

IN0SEL

Select SCT IPU input source for output channel 0.

0 (SAMPE_IN_A0_SELECT_): SAMPE_IN_A0. Select input SAMPLE_IN_A0.

1 (SAMPE_IN_B0_SELECT_): SAMPE_IN_B0. Select input SAMPLE_IN_B0.
IN1SEL

Select SCT IPU input source for output channel 1.

0 (SAMPE_IN_A1_SELECT_): SAMPE_IN_A1. Select input SAMPLE_IN_A1.

1 (SAMPE_IN_B1_SELECT_): SAMPE_IN_B1. Select input SAMPLE_IN_B1.
IN2SEL

Select SCT IPU input source for output channel 2.

0 (SAMPE_IN_A2_SELECT_): SAMPE_IN_A2. Select input SAMPLE_IN_A2.

1 (SAMPE_IN_B2_SELECT_): SAMPE_IN_B2. Select input SAMPLE_IN_B2.
IN3SEL

Select. SCT IPU input source for output channel 3.

0 (SAMPE_IN_A3_SELECT_): SAMPE_IN_A3. Select input SAMPLE_IN_A3.

1 (SAMPE_IN_B3_SELECT_): SAMPE_IN_B3. Select input SAMPLE_IN_B3.
SAMPLE_EN0SEL

Select the sample enable input as the latch/sample-enable control for the Sample_Output(0) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.

0 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(0) latch.

1 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(0) latch.

2 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(0) latch.

3 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(0) latch.
SAMPLE_EN1SEL

Select the sample enable input as the latch/sample-enable control for the Sample_Output(1) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.

0 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(1) latch.

1 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(1) latch.

2 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(1) latch.

3 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(1) latch.
SAMPLE_EN2SEL

Select the sample enable input as the latch/sample-enable control for the Sample_Output(2) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.

0 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(2) latch.

1 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(2) latch.

2 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(2) latch.

3 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(2) latch.
SAMPLE_EN3SEL

Select the sample enable input as the latch/sample-enable control for the Sample_Output(3) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.

0 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(3) latch.

1 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(3) latch.

2 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(3) latch.

3 (SELECTS_SAMPLE_ENABL): Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(3) latch.
LATCHEN0

Enable latch for output channel 0.

0 (TRANSPARENT_MODE_SA): Transparent mode. Sample_Output(0) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(0). The sample-enable control line selected for this latch has no effect.

1 (LATCHED_MODE_THE_SA): Latched mode. The Sample_Output(0) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.
LATCHEN1

Enable latch for output channel 1.

0 (TRANSPARENT_MODE_SA): Transparent mode. Sample_Output(1) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(1). The sample-enable control line selected for this latch has no effect.

1 (LATCHED_MODE_THE_SA): Latched mode. The Sample_Output(1) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.
LATCHEN2

Enable latch for output channel 2.

0 (TRANSPARENT_MODE_SA): Transparent mode. Sample_Output(2) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(2). The sample-enable control line selected for this latch has no effect.

1 (LATCHED_MODE_THE_SA): Latched mode. The Sample_Output(2) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.
LATCHEN3

Enable latch for output channel 3.

0 (TRANSPARENT_MODE_SA): Transparent mode. Sample_Output(3) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(3). The sample-enable control line selected for this latch has no effect.

1 (LATCHED_MODE_THE_SA): Latched mode. The Sample_Output(3) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data